The present invention relates to a programmable function device capable of setting the function of a circuit or the connection between circuits in various manners according to configuration data as well as to a memory cell for such a programmable function device, and more particularly to a circuit which sets configuration data in the programmable function device.
Programmable function devices such as PLDs (Programmable Logic Devices) and FPGAs (Field Programmable Gate Arrays) have been heretofore known. This kind of programmable function device is capable of setting the function of an integrated circuit in various manners according to configuration data to be loaded, and finds a wide variety of demands as a substitution for ASICs (Application Specific Integrated Circuits) having fixed functions. This kind of programmable function device is also expected as a re-configurable processor capable of providing an optimum hardware architecture according to a given problem.
A configuration circuit is a device for loading the configuration data into such a programmable function device and realizing a specific function (this procedure will be hereinafter referred to as configuration of a programmable function device).
The configuration circuit includes a plurality of configuration memories, and is disclosed in, for example, U.S. Pat. Nos. 5,430,687, 5,770,951 and 4,821,233.
As will be described later in detail, the above-described configuration circuit has the following problems.
The first problem is that the configuration memories are difficult to initialize. This is because the configuration circuit does not have the function of initializing the configuration memories.
The second problem is that a large amount of current is consumed during writing of data to the configuration memories and the speed of the writing is slow. This is because collisions occur between data signals and output signals of the configuration memories during the writing of data to the configuration memories.
An object of the present invention is, therefore, to provide a programmable function device which includes a configuration circuit having a simple initializing circuit for configuration memories.
Another object of the present invention is to provide the programmable function device including configuration memories to which data can be rapidly and reliably written with a small amount of current consumed during data writing.
The present invention is applied to a programmable function device in which one logic function is selected from among a plurality of logic functions according to data stored in a memory cell array comprised of a plurality of memory cells arranged in the form of an array. The programmable function device comprises a configuration circuit for writing data to the memory cell array.
According to a first aspect of the present invention, the configuration circuit includes at least one data shift register having a data input terminal, a plurality of data output terminals, and a clock input terminal. The data shift register is operative to serially read data through the data input terminal in synchronism with a clock signal inputted to the clock input terminal and to shift data held internally of the data shift register. The configuration circuit includes a plurality of data initializing circuits each having a first initializing input terminal, a second initializing input terminal, and an initializing output terminal. Each of the first initializing input terminals is connected to each of the plurality of data output terminals. A data initializing signal is applied to the second initializing input terminals. Each of the initializing output terminals is connected to the data input terminals of the memory cells arranged along one of columns of the memory cell array. The configuration circuit further includes an addressing circuit for selecting at least one row of the memory cell array and writing output signals of the data initializing circuits into the memory cells arranged along the selected at least one row. Each of the data initializing circuits is operative to output an initial value to be written into the memory cell array when the data initializing signal is made active, and to output a signal corresponding to a signal applied to the first initializing input terminal when the data initializing signal is made inactive.
According to a second aspect of the present invention, the configuration circuit includes at least one data shift register having a data input terminal, a plurality of data output terminals, a clock input terminal, and a clock enable terminal. The data shift register is operative to, when an input to the clock enable terminal is at its active level, serially read data through the data input terminal in synchronism with a clock signal inputted to the clock input terminal and to shift data held internally of the data shift register. The configuration circuit also includes a plurality of data initializing circuits each having a first initializing input terminal, a second initializing input terminal, and an initializing output terminal. Each of the first initializing input terminals is connected to each of the plurality of data output terminals. A data initializing signal is applied to the second initializing input terminals. Each of the initializing output terminals is connected to the data input terminals of the memory cells arranged along one of columns of the memory cell array. The configuration circuit further includes an addressing circuit for selecting at least one row of the memory cell array and writing output signals of the data initializing circuits to the memory cells arranged along the selected at least one row. Each of the data initializing circuits is operative to output an initial value to be written into the memory cell array when the data initializing signal is made active, and to output a signal corresponding to a signal applied to the first initializing input terminal when the data initializing signal is made inactive.